2026-04-17T06:27:27Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/1135782026-01-07T08:46:57Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc Amat, Esteve author Calomarde Palomino, Antonio author Canal Corretger, Ramon author Rubio Sola, Jose Antonio author 2017 This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level. Peer Reviewed Postprint (author's final draft) Àrees temàtiques de la UPC::Enginyeria electrònica Electronics FinFET eDRAM sub-VT single event upsets variability reliability. Enginyeria electrònica Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level