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   <dc:title>A systolic algorithm for the fast computation of the connected components of a graph</dc:title>
   <dc:creator>Núñez, Fernando J.</dc:creator>
   <dc:creator>Valero Cortés, Mateo</dc:creator>
   <dc:subject>Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors</dc:subject>
   <dc:subject>Parallel algorithms</dc:subject>
   <dc:subject>Multiprocessors</dc:subject>
   <dc:subject>Cellular arrays</dc:subject>
   <dc:subject>Computer architecture</dc:subject>
   <dc:subject>Multiprocessing systems</dc:subject>
   <dc:subject>Algorismes paral·lels</dc:subject>
   <dc:subject>Multiprocessadors</dc:subject>
   <dcterms:abstract>The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. The algorithm-partitioning issue is also addressed, indicating how to optimally map the computations into fixed-size rings or linear arrays. The proposed algorithm leads to simple processing elements, data addressing, and control. These points make the systolic array highly implementable.</dcterms:abstract>
   <dcterms:abstract>Peer Reviewed</dcterms:abstract>
   <dcterms:abstract>Postprint (published version)</dcterms:abstract>
   <dcterms:issued>1988</dcterms:issued>
   <dc:type>Conference report</dc:type>
   <dc:relation>http://ieeexplore.ieee.org/document/15396/</dc:relation>
   <dc:rights>Open Access</dc:rights>
   <dc:publisher>Institute of Electrical and Electronics Engineers (IEEE)</dc:publisher>
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