2026-04-14T03:51:32Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/1060172026-01-21T04:22:01Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc García Vidal, Jorge author March, Maribel author Cerdà Alabern, Llorenç author Corbal San Adrián, Jesús author Valero Cortés, Mateo author 2006-05 We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps. Peer Reviewed Postprint (published version) Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors Routing (Computer network management) Router architecture Packet buffers High-performance memory systems Storage schemes Encaminadors (Xarxes d'ordinadors) A DRAM/SRAM memory scheme for fast packet buffers