2026-04-18T04:12:11Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/1019152026-01-18T09:10:48Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc Canal Corretger, Ramon author González Colás, Antonio María author Smith, James E. author 2000 Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This significance compression method is integrated into a 5-stage pipeline, with the extension bits flowing down the pipeline to enable pipeline operations only for the significant bytes. Consequently, register logic and cache activity (and dynamic power) are substantially reduced. An initial trace-driven study shows reduction in activity of approximately 30-40% for each pipeline stage. Several pipeline organizations are studied. A byte serial pipeline is the simplest implementation, but suffers a CPI (cycles per instruction) increase of 79% compared with a conventional 32-bit pipeline. Widening certain pipeline stages in order to balance processing bandwidth leads to an implementation with a CPI 24% higher than the baseline 32-bit design. Finally, full-width pipeline stages with operand gating achieve a CPI within 2-6% of the baseline 32-bit pipeline. Peer Reviewed Postprint (published version) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors Microprocessors Cache memory Low-power electronics Pipeline processing Data compression Instruction sets Microprocessadors Memòria cau Very low power pipelines using significance compression