2026-04-17T14:22:26Zhttps://recercat.cat/oai/request
oai:recercat.cat:2117/1015182026-01-21T05:46:32Zcom_2072_1033col_2072_452950
RECERCAT author Lumbiarres López, Rubén author López García, Mariano author Cantó Navarro, Enrique 2016-09-19 This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch’s t-test and the difference of means.Peer ReviewedPostprint (author's final draft) Open Access Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica::Criptografia Cryptography Field programmable gate arrays Software-hardware countermeasures Security Side-Channel attacks Power analysis attacks Cryptography Criptografia Matrius de portes programables per l'usuari Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks Article