2026-04-17T05:16:08Zhttps://recercat.cat/oai/request

oai:recercat.cat:2099.1/226562025-07-23T05:33:58Zcom_2072_1033col_2072_452951

Improving The Robustness Of The Register File: a Register File Cache Architecture Zhuang, Sicong Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Canal Corretger, Ramon Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors Microprocessors register file process variation soft error register file process variation soft error Microprocessadors This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results. 2014-09-09 Master thesis https://hdl.handle.net/2099.1/22656 102852 eng Open Access application/pdf Universitat Politècnica de Catalunya