Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAMcell. Gate oxide scaling can cause large transient gate leakage (a trap in the gate oxide), which is known as the erratic bitsphenomena.Register file protection is necessary to prevent errors from quickly spreading to different parts of the system, which maycause applications to crash or silent data corruption. This paper proposes a simple and cost-effective mechanism that increases the resiliency of the register files to erratic bits. Our mechanism detects those registers that have erratic bits, recovers from theerror and quarantines the faulty register. After the quarantine period, it is able to detect whether they are fully operational with low overhead.

Postprint (published version)