Implicit vs. explicit resource allocation in SMT processors

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/111445

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	Cazorla Almeida, Francisco Javier
dc.contributor.author	Knijnenburg, Peter M.W.
dc.contributor.author	Sakellariou, Rizos
dc.contributor.author	Fernandez Garcia, Enrique
dc.contributor.author	Ramírez Bellido, Alejandro
dc.contributor.author	Valero Cortés, Mateo
dc.date	2004
dc.identifier.citation	Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernandez, E., Alex Ramirez, Valero, M. Implicit vs. explicit resource allocation in SMT processors. A: Euromicro Conference on Digital System Design. "2004 Euromicro Symposium on Digital Systems Design (DSD 2004)". Rennes: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 44-51.
dc.identifier.citation	0-7695-2203-3
dc.identifier.citation	10.1109/DSD.2004.1333257
dc.identifier.uri	http://hdl.handle.net/2117/111445
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	http://ieeexplore.ieee.org/document/1333257/
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Parallel processing (Electronic computers)
dc.subject	Microprocessors
dc.subject	Simultaneous multithreading processors
dc.subject	Quality of service
dc.subject	Resource allocation
dc.subject	Processament en paral·lel (Ordinadors)
dc.subject	Microprocessadors
dc.title	Implicit vs. explicit resource allocation in SMT processors
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe different resource sharing models in SMT processors. We show that explicit resource allocation can improve SMT performance. In addition, it enables SMTs to solve other QoS requirements, not realizable before.
dc.description.abstract	Peer Reviewed

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