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dc.contributor | Barcelona Supercomputing Center |
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dc.contributor.author | Slijepcevic, Mladen |
dc.contributor.author | Hernandez, Carles |
dc.contributor.author | Abella, Jaume |
dc.contributor.author | Cazorla, Francisco J. |
dc.date | 2017-05-15 |
dc.identifier.citation | Slijepcevic, M. [et al.]. Design and implementation of a fair credit-based bandwidth sharing scheme for buses. A: Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, Switzerland, Switzerland, 27-31 March 2017. "2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 926-929. |
dc.identifier.citation | 978-3-9815370-8-6 |
dc.identifier.citation | 10.23919/DATE.2017.7927122 |
dc.identifier.uri | http://hdl.handle.net/2117/104745 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7927122/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2014-60404-JIN |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/RYC-2013-14717 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Hardware |
dc.subject | Real-time data processing |
dc.subject | Multicore processing |
dc.subject | Bandwidth |
dc.subject | Real-time systems |
dc.subject | Time division multiple access |
dc.subject | Hardware |
dc.subject | Timing |
dc.subject | Context |
dc.subject | Programació en temps real |
dc.subject | Programació (Ordinadors) |
dc.title | Design and implementation of a fair credit-based bandwidth sharing scheme for buses |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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