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dc.contributor | Barcelona Supercomputing Center |
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dc.contributor.author | Milic, Ugljesa |
dc.contributor.author | Rico, Alejandro |
dc.contributor.author | Carpenter, Paul |
dc.contributor.author | Ramirez, Alex |
dc.date | 2017-07-13 |
dc.identifier.citation | Milic, U. [et al.]. Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications. A: "2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 3-12. |
dc.identifier.citation | 978-1-5386-3890-3 |
dc.identifier.citation | 10.1109/ISPASS.2017.7975265 |
dc.identifier.uri | http://hdl.handle.net/2117/106841 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7975265/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/BES2013-063925 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | High performance computing |
dc.subject | Cache memory |
dc.subject | Multicore processing |
dc.subject | Benchmark testing |
dc.subject | Prefetching |
dc.subject | Hardware |
dc.subject | Proposals |
dc.subject | Throughput |
dc.subject | Supercomputadors |
dc.title | Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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