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Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications
Milic, Ugljesa; Rico, Alejandro; Carpenter, Paul; Ramirez, Alex
Barcelona Supercomputing Center
Àrees temàtiques de la UPC::Enginyeria electrònica
High performance computing
Cache memory
Multicore processing
Benchmark testing
Prefetching
Hardware
Proposals
Throughput
Supercomputadors
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/submittedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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