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dc.contributor | Barcelona Supercomputing Center |
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dc.contributor.author | Serrano, Maria A. |
dc.contributor.author | Melani, Alessandra |
dc.contributor.author | Kehr, Sebastian |
dc.contributor.author | Bertogna, Marko |
dc.contributor.author | Quiñones, Eduardo |
dc.date | 2017-07-03 |
dc.identifier.citation | Serrano, M. A. [et al.]. An Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling. A: "2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 193-202. |
dc.identifier.citation | 978-1-5386-1574-4 |
dc.identifier.citation | 10.1109/ISORC.2017.9 |
dc.identifier.uri | http://hdl.handle.net/2117/107002 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7964887/ |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/688860/EU/High-Performance Real-time Architectures for Low-Power Embedded Systems/HERCULES |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria elèctrica |
dc.subject | Computers--Research |
dc.subject | Parallel programming (Computer science) |
dc.subject | Computational modeling |
dc.subject | Interference |
dc.subject | Real-time systems |
dc.subject | Processor scheduling |
dc.subject | Computer architecture |
dc.subject | Analytical models |
dc.subject | Parallel programming |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Ordinadors--Dispositius de memòria |
dc.title | An Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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