Partitioning: an essential step in mapping algorithms into systolic array processors

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Title:	Partitioning: an essential step in mapping algorithms into systolic array processors
Author:	Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo
Other authors:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Abstract:	The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal -Systolic array circuits -Partitioning algorithms -Systolic arrays -Signal processing algorithms -Equations -Fault tolerant systems -Computational modeling -Design methodology -Hardware -Digital signal processing -Algorithm design and analysis -Processadors de matrius (arrays)
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Document type:	Article - Published version Article
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