A DRAM/SRAM memory scheme for fast packet buffers

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/106017

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	García Vidal, Jorge
dc.contributor.author	March, Maribel
dc.contributor.author	Cerdà Alabern, Llorenç
dc.contributor.author	Corbal San Adrián, Jesús
dc.contributor.author	Valero Cortés, Mateo
dc.date	2006-05
dc.identifier.citation	García, J., March, M., Cerdà, L., Corbal, J., Valero, M. A DRAM/SRAM memory scheme for fast packet buffers. "IEEE transactions on computers", Maig 2006, vol. 55, núm. 5, p. 588-602.
dc.identifier.citation	0018-9340
dc.identifier.citation	10.1109/TC.2006.63
dc.identifier.uri	http://hdl.handle.net/2117/106017
dc.language.iso	eng
dc.relation	http://ieeexplore.ieee.org/document/1613839/
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subject	Routing (Computer network management)
dc.subject	Router architecture
dc.subject	Packet buffers
dc.subject	High-performance memory systems
dc.subject	Storage schemes
dc.subject	Encaminadors (Xarxes d'ordinadors)
dc.title	A DRAM/SRAM memory scheme for fast packet buffers
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.
dc.description.abstract	Peer Reviewed

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