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Title:
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A DRAM/SRAM memory scheme for fast packet buffers
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Author:
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García Vidal, Jorge; March, Maribel; Cerdà Alabern, Llorenç; Corbal San Adrián, Jesús; Valero Cortés, Mateo
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
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Abstract:
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We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
-Routing (Computer network management)
-Router architecture
-Packet buffers
-High-performance memory systems
-Storage schemes
-Encaminadors (Xarxes d'ordinadors) |
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Rights:
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Document type:
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Article - Published version
Article |
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