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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Pericàs Gleim, Miquel |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Cazorla, Francisco |
dc.contributor.author | González García, Rubén |
dc.contributor.author | Veidenbaum, Alexander V |
dc.contributor.author | Jiménez, Daniel A. |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2008 |
dc.identifier.citation | Pericàs, M., Cristal, A., Cazorla, F., González, R., Veidenbaum, A.V., Jiménez, D. A., Valero, M. A two level load/store queue based on execution locality. A: International Symposium on Computer Arquitecture. "ISCA 2008 Proceedings: 35th International Symposium on Computer Architecture: 21-25 June 2008, Beijing, China". Beijing: Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 25-36. |
dc.identifier.citation | 978-0-7695-3174-8 |
dc.identifier.citation | 10.1109/ISCA.2008.10 |
dc.identifier.uri | http://hdl.handle.net/2117/105883 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/4556713/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Parallel processing |
dc.subject | Cache storage |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | A two level load/store queue based on execution locality |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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