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Virtual registers
González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) for each operation that has a destination register. When an instruction is committed, it frees the physical register allocated to the previous instruction that had the same destination logical register. Thus, an additional register (i.e. in addition to the number of logical registers) is used for each instruction with a destination register from the time it is decoded until it is committed. In this paper, we propose a novel register organization that allocates physical registers when instructions complete their execution. In this way, the register pressure is significantly reduced, since the additional register is only used from the time execution completes until the instruction is committed. For some long-latency instructions (e.g. load with a cache miss) and for parts of the code with a small amount of parallelism, the savings could be very high. We have evaluated the new scheme for a superscalar processor and obtained a significant speedup.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Multiprocessors
Computer architecture
Multiprocessing systems
Virtual storage
Decoding
Storage allocation
Multiprocessadors
Arquitectura d'ordinadors
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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