Title:
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Modelling the confidence of timing analysis for time randomised caches
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Author:
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Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Timing is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however complicates timing analysis. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at analysing the timing behaviour of ERTS deploying complex hardware features such as caches. A key parameter for MBPTA to
provide reliable results is the number of runs to perform to ensure probabilistic representativeness of the execution time measurements taken at analysis time with respect to execution times that can occur during system operation. In this paper, focusing on the cache-acknowledged as one of the most complex resources to time analyse-we address the problem of determining whether the number of observations taken at analysis, as part of the normal MBPTA application process, captures the cache events significantly impacting execution time and Worst-Case Execution Time (WCET). If this is not the case, our techniques provide the user with the number of extra runs to perform to guarantee that those cache events are captured ensuring confidence on provided WCET estimates. |
Abstract:
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The research leading to these results has received funding from the European Community’s Seventh Framework Programme [FP7/2007-2013] under the PROXIMA Project
(www.proxima-project.eu), grant agreement no 611085. This work was also supported by the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P, the HiPEAC
Network of Excellence. Jaume Abella was partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship (RYC-2013-14717). |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Cache memory -Embedded computer systems -Timing -Reliability -Hardware -Standards -Safety -Probabilistic logic -Memòria ràpida de treball (Informàtica) -Ordinadors immersos, Sistemes d' |
Rights:
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Document type:
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Article - Submitted version Conference Object |
Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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