dc.contributor |
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor |
Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author |
Zyulkyarov, Ferad Hasanov |
dc.contributor.author |
Cvijic, Sanja |
dc.contributor.author |
Unsal, Osman Sabri |
dc.contributor.author |
Cristal Kestelman, Adrián |
dc.contributor.author |
Ayguadé Parra, Eduard |
dc.contributor.author |
Harris, Tim |
dc.contributor.author |
Valero Cortés, Mateo |
dc.date |
2008-08 |
dc.identifier.citation |
Zyulkyarov, F., Cvijic, S., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., Valero, M. "WormBench: technical report". 2008. |
dc.identifier.uri |
http://hdl.handle.net/2117/104850 |
dc.language.iso |
eng |
dc.relation |
UPC-DAC-RR-CAP-2008-23 |
dc.rights |
info:eu-repo/semantics/openAccess |
dc.subject |
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject |
Simultaneous multithreading processors |
dc.subject |
Parallel programming (Computer science) |
dc.subject |
Transactional memory |
dc.subject |
Benchmarck |
dc.subject |
Parallel application |
dc.subject |
Programació en paral·lel (Informàtica) |
dc.subject |
Multiprocessadors |
dc.title |
WormBench: technical report |
dc.type |
info:eu-repo/semantics/publishedVersion |
dc.type |
info:eu-repo/semantics/report |
dc.description.abstract |
Transactional Memory (TM) is a promising new technology that makes it possible to ease writing multi-threaded applications. Many different TM implementations exist, unfortunately most of those TM systems are currently evaluated by using workloads that are (1) tightly coupled to the interface of a particular TM implementation, (2) are small and lack to capture the common concurrency problems that exist in real multi-threaded applications and also (3) fail to evaluate the overall behavior of the Transactional Memory system within the context of the computer system from micro-architectural level up to the programming language support.
WormBench is parameterized workload designed from the ground up to evaluate Transactional Memory systems in terms of robustness and performance. Its goal is to provide a unified solution to the problems stated above (1, 2, 3). The critical sections in the code are marked with the atomic statements and thus proving a framework to test the compiler or language interpreter ability to translate them properly and efficiently into the appropriate TM system interface. Its design considers all the common synchronization problems that exist in TM multi-threaded applications. The overall behavior of WormBench can be changed by using run configurations which provide the ability to reproduce a runtime behavior observed in a typical multi-threaded application or a behavior that stresses a particular aspect of the TM system such as abort handling. In this paper, we analyze the transactional characteristics of WormBench by studying different run configurations and demonstrate how WormBench can be configured so that it has similar TM behavior with an existing transactional application from the STAMP TM application suite. |