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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Papandroulikadis, Georgios |
dc.contributor.author | Vourkas, Ioannis |
dc.contributor.author | Abustelema, Angel |
dc.contributor.author | Sirakoulis, Georgios |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.date | 2017-04-01 |
dc.identifier.citation | Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. |
dc.identifier.citation | 1536-125X |
dc.identifier.citation | 10.1109/TNANO.2017.2691713 |
dc.identifier.uri | http://hdl.handle.net/2117/104473 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/document/7893787/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TEC2013-45638-C3-2-R |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics |
dc.subject | Memristors |
dc.subject | Microelectromechanical systems |
dc.subject | Electric switchgear |
dc.subject | Nonvolatile random-access memory |
dc.subject | Computing |
dc.subject | Crossbar |
dc.subject | Digital logic |
dc.subject | Memristor |
dc.subject | |
dc.subject | Resistive RAM (ReRAM) |
dc.subject | Resistive switch |
dc.subject | Memòria d'accés aleatori |
dc.subject | Sistemes microelectromecànics |
dc.subject | Semiconductors de commutació |
dc.title | Crossbar-based memristive logic-in-memory architecture |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
dc.description.abstract |