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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Chronaki, Kallia |
dc.contributor.author | Moreto Planas, Miquel |
dc.contributor.author | Casas Guix, Marc |
dc.contributor.author | Rico, Alejandro |
dc.contributor.author | Badia Sala, Rosa Maria |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2016 |
dc.identifier.citation | Chronaki, K., Moreto, M., Casas, M., Rico, A., Badia, R.M., Ayguadé, E., Labarta, J., Valero, M. POSTER: Exploiting asymmetric multi-core processors with flexible system sofware. A: International Conference on Parallel Architectures and Compilation Techniques. "PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation". Haifa: Association for Computing Machinery (ACM), 2016, p. 415-417. |
dc.identifier.citation | 978-1-4503-4121-9 |
dc.identifier.citation | 10.1145/2967938.2976038 |
dc.identifier.uri | http://hdl.handle.net/2117/96641 |
dc.language.iso | eng |
dc.publisher | Association for Computing Machinery (ACM) |
dc.relation | http://dl.acm.org/citation.cfm?doid=2967938.2976038 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/610402/EU/Mont-Blanc 2, European scalable and power efficient HPC platform based onlow-power embedded technology/MONT-BLANC 2 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology/Mont-Blanc 3 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | High performance computing -- Energy conservation |
dc.subject | Energy conservation |
dc.subject | Energy efficiency |
dc.subject | Memory architecture |
dc.subject | Parallel architectures |
dc.subject | Parallel processing systems |
dc.subject | Scheduling |
dc.subject | Cache coherence |
dc.subject | Dynamic scheduling |
dc.subject | Efficient scheduling |
dc.subject | High performance computin (HPC) |
dc.subject | Memory consistency |
dc.subject | Multi-core processor |
dc.subject | Multicore architectures |
dc.subject | Parallel application |
dc.subject | Càlcul intensiu (Informàtica) -- Estalvi d'energia |
dc.title | POSTER: Exploiting asymmetric multi-core processors with flexible system sofware |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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