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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Caheny, Paul |
dc.contributor.author | Casas, Marc |
dc.contributor.author | Moreto Planas, Miquel |
dc.contributor.author | Gloaguen, Hervé |
dc.contributor.author | Saintes, Maxime |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2016 |
dc.identifier.citation | Caheny, P., Casas, M., Moreto, M., Gloaguen, H., Saintes, M., Ayguadé, E., Labarta, J., Valero, M. Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling. A: International Conference on Parallel Architectures and Compilation Techniques. "PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation". Haifa: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 275-286. |
dc.identifier.citation | 978-1-4503-4121-9 |
dc.identifier.citation | 10.1145/2967938.2967962 |
dc.identifier.uri | http://hdl.handle.net/2117/96470 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://dl.acm.org/citation.cfm?id=2967962 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology/Mont-Blanc 3 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation | info:eu-repo/grantAgreement/ES/SEV-2015-0493 |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology/Mont-Blanc 3 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Memory management (Computer science) |
dc.subject | Cache memory |
dc.subject | Cache coherence |
dc.subject | NUMA |
dc.subject | Task-based programming models |
dc.subject | Gestió de memòria (Informàtica) |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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