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High-Level Debugging and Verification for FPGA-Based Multicore Architectures
Arcas, Oriol; Cristal, Adrian; Unsal, Osman S.
Barcelona Supercomputing Center
Simulators are key tools for computer architecture research. However, multicore architectures represent a highly complex challenge for software simulators, which may suffer from fidelity loss and long execution times. FPGAs can simulate multicore architectures with scalable performance and high accuracy, but the difficulty of debugging could hinder their adoption. In this paper we propose several techniques for inspection, debugging and verification of multicore architectures, both for software-based and FPGA-based simulations. These debugging extensions are cycle-accurate and unobtrusive. As a proof of concept, we have developed a 24-core RISC multiprocessor that runs the Linux Kernel, for which we provide three simulation modes: a fast, functional simulation; a detailed, cycle-accurate simulation; and a FPGA-based simulation. Our platform can run up to 24 cores and perform full-system verification at 17 million instructions per second.
Peer Reviewed
Àrees temàtiques de la UPC::Enginyeria electrònica
Debugging in computer science
Computer architecture
FPGA
Computer simulation
FPGA
Debugging
Verification
Multicore
Simulació, Mètodes de
Simulació per ordinador
Multiprocessadors
Arquitectura d'ordinadors
info:eu-repo/semantics/submittedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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