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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Aragón, Juan Luis |
dc.contributor.author | González, José |
dc.contributor.author | García Carrasco, José M. |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2001 |
dc.identifier.citation | Aragón, J., González, J., García, J., González, A. Selective branch prediction reversal by correlating with data values and control flow. A: IEEE International Conference on Computer Design. "2001 International Conference on Computer Design, ICCD 2001: 23-26 September 2001 Austin, Texas, USA: proceedings". Austin, TX: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 228-233. |
dc.identifier.citation | 0-7695-1200-3 |
dc.identifier.citation | 10.1109/ICCD.2001.955033 |
dc.identifier.uri | http://hdl.handle.net/2117/102017 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/955033/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Performance evaluation |
dc.subject | Parallel architectures |
dc.subject | Pipeline processing |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Selective branch prediction reversal by correlating with data values and control flow |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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