Títol:
|
Hardware schemes for early register release
|
Autor/a:
|
Monreal Arnal, Teresa; Viñals Yufera, Víctor; González Colás, Antonio María; Valero Cortés, Mateo
|
Altres autors:
|
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
|
Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the size and number of ports of the register file. In conventional register renaming schemes, register releasing is conservatively done only after the instruction that redefines the same register is committed. Instead, we propose a scheme that releases registers as soon as the processor knows that there will be no further use of them. We present two early releasing hardware implementations with different performance/complexity trade-offs. Detailed cycle-level simulations show either a significant speedup for a given register file size, or a reduction in register file size for a given performance level. |
Abstract:
|
Peer Reviewed |
Matèries:
|
-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Microprocessors -Hardware -Registers -Timing -Decoding -Out of order -Concurrent computing -Parallel processing -Counting circuits -Gain measurement -Proposals -Microprocessadors |
Drets:
|
|
Tipus de document:
|
Article - Versió publicada Objecte de conferència |
Publicat per:
|
Institute of Electrical and Electronics Engineers (IEEE)
|
Compartir:
|
|