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Random Modulo: A new processor cache design for real-time critical systems
Hernández, Carles; Abella Ferrer, Jaume; Gianarro, Andrea; Andersson, Jan; Cazorla Almeida, Francisco Javier
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, caches complicate timing analysis. In the context of Measurement-Based Probabilistic Timing Analysis (MBPTA) - a promising technique to ease timing analyis of complex hardware - we propose Random Modulo (RM), a new cache design that provides the probabilistic behavior required by MBPTA and with the following advantages over existing MBPTA-compliant cache designs: (i) an outstanding reduction in WCET estimates, (ii) lower latency and area overhead, and (iii) competitive average performance w.r.t conventional caches.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Cache memory
Cache memories
Measurement-Based Probabilistic Timing Analysis (MBPTA)
Random Modulo (RM)
Memòria ràpida de treball (Informàtica)
info:eu-repo/semantics/submittedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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