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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Jalle Ibarra, Javier |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Abella, Jaume |
dc.contributor.author | Fossati, Luca |
dc.contributor.author | Zulianello, Marco |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.date | 2016 |
dc.identifier.citation | Jalle, J., Quiñones, E., Abella, J., Fossati, L., Zulianello, M., Cazorla, F. Data bus slicing for contention-free multicore real-time memory systems. A: IEEE International Symposium on Industrial Embedded Systems. "2016 11th IEEE International Symposium on Industrial Embedded Systems (SIES): Krakow, Poland 23-25 May 2016: proceedings". Krakow: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-8. |
dc.identifier.citation | 978-1-5090-2282-3 |
dc.identifier.citation | 10.1109/SIES.2016.7509441 |
dc.identifier.uri | http://hdl.handle.net/2117/97165 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7509441/?arnumber=7509441 |
dc.relation | info:eu-repo/grantAgreement/ES/RYC-2013-14717 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Real-time data processing |
dc.subject | Multiprocessors -- Programming |
dc.subject | Buses |
dc.subject | Embedded systems |
dc.subject | Memory architecture |
dc.subject | System buses |
dc.subject | Contention-free |
dc.subject | Control memory |
dc.subject | Memory access |
dc.subject | Memory locality |
dc.subject | Memory organizations |
dc.subject | Memory systems |
dc.subject | Time variability |
dc.subject | Timing Analysis |
dc.subject | Temps real (Informàtica) |
dc.subject | Multiprocessadors -- Programació |
dc.title | Data bus slicing for contention-free multicore real-time memory systems |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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