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dc.contributor | Barcelona Supercomputing Center |
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dc.contributor.author | Asifuzzaman, Kazi |
dc.contributor.author | Pavlovic, Milan |
dc.contributor.author | Radulovic, Milan |
dc.contributor.author | Zaragoza, David |
dc.contributor.author | Kwon, Ohseong |
dc.contributor.author | Ryoo, Kyung-Chang |
dc.contributor.author | Radojkovic, Petar |
dc.date | 2016-10 |
dc.identifier.citation | Asifuzzaman, Kazi [et al.]. Performance impact of a slower main memory: a case study of STT-MRAM in HPC. A: MEMSYS '16. "Proceedings of the Second International Symposium on Memory Systems". ACM, 2016, p. 40-49. |
dc.identifier.citation | 978-1-4503-4305-3 |
dc.identifier.citation | 10.1145/2989081.2989082 |
dc.identifier.uri | http://hdl.handle.net/2117/91091 |
dc.language.iso | eng |
dc.publisher | ACM |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/671578/EU/European Exascale Processor Memory Node Design/ExaNoDe |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Processors, High performance |
dc.subject | Supercomputers--Programming |
dc.subject | Memory--Computer simulation |
dc.subject | Processors and memory architectures |
dc.subject | Non-volatile memory |
dc.subject | Massively parallel and high-performance simulations |
dc.subject | STT-MRAM |
dc.subject | Main memory |
dc.subject | High-performance computing |
dc.subject | Ordinadors--Dispositius de memòria |
dc.subject | Supercomputadors |
dc.title | Performance impact of a slower main memory: a case study of STT-MRAM in HPC |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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