Synthesis of timing paths with delays adaptable to integrated circuit variability

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dc.contributor	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor	Cortadella, Jordi
dc.contributor.author	Moreno Vega, Alberto
dc.date	2015-07-10
dc.identifier.citation	109546
dc.identifier.uri	http://hdl.handle.net/2117/81051
dc.language.iso	eng
dc.publisher	Universitat Politècnica de Catalunya
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica
dc.subject	Integrated circuits
dc.subject	variabilitat
dc.subject	camí crític
dc.subject	process corner
dc.subject	beam search
dc.subject	ring oscillator
dc.subject	rellotges adaptatius
dc.subject	llibreria de standard cells
dc.subject	Variability
dc.subject	critical path
dc.subject	process corner
dc.subject	adaptive clocks
dc.subject	standard cell library
dc.subject	Circuits integrats
dc.title	Synthesis of timing paths with delays adaptable to integrated circuit variability
dc.type	info:eu-repo/semantics/masterThesis
dc.description.abstract	This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage.