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dc.contributor | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
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dc.contributor | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Galcerán Oms, Marc |
dc.contributor.author | Kishinevsky, Mike |
dc.contributor.author | Sapatnekar, Sachin S. |
dc.date | 2015-11-01 |
dc.identifier.citation | Cortadella, J., Galceran, M., Kishinevsky, M., Sapatnekar, S. RTL synthesis: From logic synthesis to automatic pipelining. "Proceedings of the IEEE", 01 Novembre 2015, vol. 103, núm. 11, p. 2061-2075. |
dc.identifier.citation | 0018-9219 |
dc.identifier.citation | 10.1109/JPROC.2015.2456189 |
dc.identifier.uri | http://hdl.handle.net/2117/82027 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275092 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2013-46181-C2-1-R |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject | Semiconductor industry |
dc.subject | Logic design |
dc.subject | Design automation |
dc.subject | Logic synthesis |
dc.subject | High-level synthesis |
dc.subject | Architectural pipelining |
dc.subject | Timing elasticity |
dc.subject | Semiconductors -- Indústria i comerç |
dc.subject | Estructura lògica |
dc.title | RTL synthesis: From logic synthesis to automatic pipelining |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
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