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RTL synthesis: From logic synthesis to automatic pipelining
Cortadella Fortuny, Jordi; Galcerán Oms, Marc; Kishinevsky, Mike; Sapatnekar, Sachin S.
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.
Peer Reviewed
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
Semiconductor industry
Logic design
Design automation
Logic synthesis
High-level synthesis
Architectural pipelining
Timing elasticity
Semiconductors -- Indústria i comerç
Estructura lògica
info:eu-repo/semantics/submittedVersion
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