Topic 7: parallel computer architecture and instruction level parallelism

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Title:	Topic 7: parallel computer architecture and instruction level parallelism
Author:	Ayguadé Parra, Eduard; Wolfgang, Kark; De Bosschere, Koen; Francois, Jean Collard
Other authors:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Abstract:	We welcome you to the two Parallel Computer Architecture and Instruction Level Parallelism sessions of Euro-Par 2006 conference being held in Dresden, Germany. The call for papers for this Euro-Par topic area sought papers on all hardware/software aspects of parallel computer architecture, processor architecture and microarchitecture. This year 12 papers were submitted to this topic area. Among the submissions, 5 papers were accepted as full papers for the conference (41% acceptance rate).
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Informàtica -Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles -Parallel programming (Computer science) -Programació en paral·lel (Informàtica)
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Article
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