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| dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
|---|---|
| dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.contributor.author | Vujic, N |
| dc.contributor.author | González Tallada, Marc |
| dc.contributor.author | Martorell Bofill, Xavier |
| dc.contributor.author | Ayguadé Parra, Eduard |
| dc.date | 2008-01 |
| dc.identifier.citation | Vujic, N. [et al.]. Automatic pre-fetch and modulo scheduling transformations for the cell BE architecture. "Lecture notes in computer science", Gener 2008, vol. 5335, p. 31-46. |
| dc.identifier.citation | 0302-9743 |
| dc.identifier.citation | 10.1007/978-3-540-89740-8_3 |
| dc.identifier.uri | http://hdl.handle.net/2117/28406 |
| dc.description.abstract | Ease of programming is one of the main impediments for the broad acceptance of multi-core systems with no hardware support for transparent data transfer between local and global memories. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this paper, we propose a hierarchical, hybrid software-cache architecture that targets enabling pre-fetch techniques. Memory accesses are classified at compile time in two classes, high-locality and irregular. Our approach then steers the memory references toward one of two specific cache structures optimized for their respective access pattern. The specific cache structures are optimized to enable high-level compiler optimizations to aggressively unroll loops, reorder cache references, and/or transform surrounding loops so as to practically eliminate the software cache overhead in the innermost loop. The cache design enables automatic pre-fetch and modulo scheduling transforma-tions. Performance evaluation indicates that the optimized software-cache structures combined with the proposed pre-fetch techniques translate into speed-up between 10% and 20%. Evaluation is done on a set of parallel NAS applications. Languages and Compilers for Parallel Computing Languages and Compilers for Parallel Computing Look Inside Other actions Reprints and Permissions Export citation About this Book Add to Papers Share Share this content on Facebook Share this content on Twitter Share this content on LinkedIn |
| dc.description.abstract | Peer Reviewed |
| dc.language.iso | eng |
| dc.relation | http://link.springer.com/chapter/10.1007%2F978-3-540-89740-8_3 |
| dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
| dc.rights | info:eu-repo/semantics/openAccess |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject | Multiprocessors |
| dc.subject | Cell BE architecture |
| dc.subject | Software cache |
| dc.subject | Pre-fetching |
| dc.subject | Modulo scheduling |
| dc.subject | Multiprocessadors |
| dc.title | Automatic pre-fetch and modulo scheduling transformations for the cell BE architecture |
| dc.type | info:eu-repo/semantics/publishedVersion |
| dc.type | info:eu-repo/semantics/article |
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