Timing verification of fault-tolerant chips for safety-critical applications in harsh environments

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.author	Slijepcevic, Mladen
dc.contributor.author	Kosmidis, Leonidas
dc.contributor.author	Abella Ferrer, Jaume
dc.contributor.author	Quiñones, Eduardo
dc.contributor.author	Cazorla, Francisco J.
dc.date	2014-11-01
dc.identifier.citation	Slijepcevic, M. [et al.]. Timing verification of fault-tolerant chips for safety-critical applications in harsh environments. "IEEE micro", 01 Novembre 2014, vol. 34, núm. 6, p. 7-18.
dc.identifier.citation	0272-1732
dc.identifier.citation	10.1109/MM.2014.59
dc.identifier.uri	http://hdl.handle.net/2117/27520
dc.language.iso	eng
dc.relation	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6853246
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights	info:eu-repo/semantics/openAccess
dc.rights	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Informàtica
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject	Fault-tolerant computing
dc.subject	Embedded computer systems
dc.subject	Systems
dc.subject	Caches
dc.subject	Embedded systems
dc.subject	Fault tolerant computing
dc.subject	Formal verification
dc.subject	Parallel processing
dc.subject	Program diagnostics
dc.subject	Safety-critical software
dc.subject	Tolerància als errors (Informàtica)
dc.subject	Sistemes incrustats (Informàtica)
dc.title	Timing verification of fault-tolerant chips for safety-critical applications in harsh environments
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and architectures challenges time predictability and reliability. The authors propose a new approach to obtain trustworthy worst-case execution time estimates for safety-critical applications running on high-performance faulty hardware by using both timing-analysis techniques and minor hardware modifications.
dc.description.abstract	Peer Reviewed

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