Timing verification of fault-tolerant chips for safety-critical applications in harsh environments

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Title:	Timing verification of fault-tolerant chips for safety-critical applications in harsh environments
Author:	Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla, Francisco J.
Other authors:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Abstract:	Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and architectures challenges time predictability and reliability. The authors propose a new approach to obtain trustworthy worst-case execution time estimates for safety-critical applications running on high-performance faulty hardware by using both timing-analysis techniques and minor hardware modifications.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Informàtica -Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles -Fault-tolerant computing -Embedded computer systems -Systems -Caches -Embedded systems -Fault tolerant computing -Formal verification -Parallel processing -Program diagnostics -Safety-critical software -Tolerància als errors (Informàtica) -Sistemes incrustats (Informàtica)
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Article
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