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A crosstalk latch circuit design
Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions; Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies
A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen
Peer Reviewed
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
Integrated circuits
CMOS integrated circuits
VLSI
Crosstalk
Digital integrated circuits
Flip-flops
Circuits integrats
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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