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Reducing compiler-inserted instrumentation in unified-parallel-C code generation
Alvanos, Michail; Amaral, José Nelson; Tiotto, Ettore; Farreras Esclusa, Montserrat; Martorell Bofill, Xavier
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d´Altes Prestacions
Programs written in Partitioned Global Address Space (PGAS) languages can access any location of the entire address space via standard read/write operations. However, the compiler have to create the communication mechanisms and the runtime system to use synchronization primitives to ensure the correct execution of the programs. However, PGAS programs may have fine-grained shared accesses that lead to performance degradation. One solution is to use the inspector-executor technique to determine which accesses are indeed remote and which accesses may be coalesced in larger remote access operations. A straightforward implementation of the inspector-executor in a PGAS system may result in excessive instrumentation that hinders performance. This paper introduces a shared-data localization transformation based on linear memory descriptors (LMADs) that reduces the amount of instrumentation introduced by the compiler into programs written in the UPC language and describes a prototype implementation of the proposed transformation. A performance evaluation, using up to 2048 cores of a POWER 775 supercomputer, allows for a prediction that applications with regular accesses can achieve up to 180% of the performance of handoptimized versions while applications with irregular accesses yield performance gain from 1.12X up to 6.3X speedup.
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
Àrees temàtiques de la UPC::Informàtica::Llenguatges de programació
Parallel processing (Electronic computers)
Programming languages (Electronic computers)
Computer architecture
Linear transformations
Mathematical transformations
Metadata
Program compilers
Supercomputers Communication mechanisms
Data localization
Partitioned Global Address Space
Performance degradation
Prototype implementations
Read/write operations
Synchronization primitive
Transformation based
Processament en paral·lel (Ordinadors)
Llenguatges de programació
info:eu-repo/semantics/publishedVersion
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Institute of Electrical and Electronics Engineers (IEEE)
         

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