Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/25262

Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design
Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the memory cells using an adaptive strategy. To track the aging in the SRAM cells we propose an on-chip monitoring technique. Our results show the technique as a feasible way to extend the cache lifetime up to 5X.
Peer Reviewed
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
Random access memory
Memòria d'accés aleatori
info:eu-repo/semantics/submittedVersion
Artículo
         

Mostrar el registro completo del ítem

Documentos relacionados

Otros documentos del mismo autor/a

Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio
Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio
Pouyan, Peyman; Amat Bertran, Esteve; Barajas Ojeda, Enrique; Rubio Sola, Jose Antonio