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On the selection of adder unit in energy efficient vector processing
Ratkovic, Ivan; Palomar Pérez, Óscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Àrees temàtiques de la UPC::Informàtica
Microprocessors
Logic design
Adders
Logic design
Microprocessor chips
Microprocessadors
Estructura lògica
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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