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Library-free technology mapping for VLSI circuits with regular layouts
Alvarez Ruiz, Alex
Universitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics; Cortadella Fortuny, Jordi; Sapatnekar, Sachin
Technology mapping is the task to transform a technology independent logic network into a mapped network using gates from a library, optimizing some objective function such total area, delay or power consumption. As stated, the problem is completely intractable. Therefore, different techniques are applied to solve the problem, such as using different simplified representations. The usual approach consists of using a fixed library, typically partially handmade. Designing such libraries is a costly process, specially because of the lack of good automatic techniques to perform it. This is the main motivation for this work and the goal is to move from fixed-library technology mapping to library-free technology mapping. This thesis presents different algorithms and techniques to move to library-free technology mapping for area and for delay optimization
Àrees temàtiques de la UPC::Matemàtiques i estadística::Matemàtica discreta
Algorithms
Algorithms
Technology mapping
Graphs
Optimization
Algorismes
Classificació AMS::68 Computer science::68W Algorithms
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/masterThesis
Universitat Politècnica de Catalunya
         

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