The use of dual-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells is presented as a candidate topology for integrated power management to obtain favorable tradeoffs in terms of efficiency, switching ripple, and bandwidth. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency and low output ripples, simultaneously. A comparison analysis is done with regards to the aforementioned performance indexes with the standard and three-level buck converters and the results are validated in HSPICE in a 0.35 µm CMOS process.

Peer Reviewed