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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Kumar, Rakesh |
dc.contributor.author | Martínez, Alejandro |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2013 |
dc.identifier.citation | Kumar, R.; Martínez, A.; González, A. Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment. A: International Symposium on Computer Architecture and High Performance Computing. "2013 25th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2013: 23-26 October 2013, Porto de Galinhas, PE, Brazil: proceeding". Porto de Galinhas, Pernambuco: IEEE Computer Society Publications, 2013, p. 81-88. |
dc.identifier.citation | 978-1-4799-2927-6 |
dc.identifier.citation | 10.1109/SBAC-PAD.2013.10 |
dc.identifier.uri | http://hdl.handle.net/2117/23295 |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | System design |
dc.subject | HW/SW co-designed processor |
dc.subject | Devectorization |
dc.subject | Power gating |
dc.subject | Leakage |
dc.subject | Microprocessadors |
dc.subject | Disseny de sistemes |
dc.title | Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |