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Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment
Kumar, Rakesh; Martínez, Alejandro; González Colás, Antonio María
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
Leakage power is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this power. Therefore, reducing functional unit leakage has received much attention in the recent years. Power gating is one of the most widely used techniques to minimize leakage energy. Power gating turns off the functional units during the idle periods to reduce the leakage. Therefore, the amount of leakage energy savings is directly proportional to the idle time duration. This paper focuses on increasing the idle interval for the higher SIMD lanes. The applications are profiled dynamically, in a HW/SW co-designed environment, to find the higher SIMD lanes usage pattern. If the higher lanes need to be turned-on for small time periods, the corresponding portion of the code is devectorized to keep the higher lanes off. The devectorized code is executed on the lowest SIMD lane. Our experimental results show average SIMD accelerator energy savings of 12% and 24% relative to power gating, for SPECFP2006 and Physicsbench. Moreover, the slowdown caused due to devectorization is less than 1%.
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Microprocessors
System design
HW/SW co-designed processor
Devectorization
Power gating
Leakage
Microprocessadors
Disseny de sistemes
info:eu-repo/semantics/submittedVersion
info:eu-repo/semantics/conferenceObject
IEEE Computer Society Publications
         

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