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FPGA implementation of a PWM for a three-phase DC-AC multilevel active-clamped converter
Lupón Roses, Emilio; Busquets Monge, Sergio; Nicolás Apruzzese, Joan
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades; Universitat Politècnica de Catalunya. GREP - Grup de Recerca en Electrònica de Potència
With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGA-based modulator
Àrees temàtiques de la UPC::Enginyeria electrònica::Optoelectrònica
Electronic circuits
Field-programmable gate array (FPGA)
multilevel active-clamped (MAC) converter
pulsewidth modulation (PWM)
Circuits electrònics
info:eu-repo/semantics/publishedVersion
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