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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Garcia, Marina |
dc.contributor.author | Vallejo, Enrique |
dc.contributor.author | Beivide Palacio, Julio Ramón |
dc.contributor.author | Odriozola, Miguel |
dc.contributor.author | Camarero Coterillo, Cristobal |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Rodríguez, Germán |
dc.date | 2013 |
dc.identifier.citation | Garcia, M. [et al.]. Global misrouting policies in two-level hierarchical networks. A: International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. "Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip". Berlin: 2013, p. 13-16. |
dc.identifier.citation | 9781450317849 |
dc.identifier.citation | 10.1145/2482759.2482763 |
dc.identifier.uri | http://hdl.handle.net/2117/23136 |
dc.language.iso | eng |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject | Routing (Computer network management) |
dc.subject | Network routing |
dc.subject | Interconnection networks |
dc.subject | Network architecture |
dc.subject | Routers |
dc.subject | Encaminadors (Xarxes d'ordinadors) |
dc.title | Global misrouting policies in two-level hierarchical networks |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |