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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor.author | Kosmidis, Leonidas |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.date | 2013 |
dc.identifier.citation | Kosmidis, L. [et al.]. A cache design for probabilistically analysable real-time systems. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013". Grenoble: 2013, p. 513-518. |
dc.identifier.citation | 978-398153700-0 |
dc.identifier.uri | http://hdl.handle.net/2117/22448 |
dc.language.iso | eng |
dc.relation | http://dl.acm.org/citation.cfm?id=2485288.2485416 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject | Embedded computer systems |
dc.subject | Fault-tolerant computing |
dc.subject | Amount of information |
dc.subject | Cache access |
dc.subject | Hardware complexity |
dc.subject | Hardware design |
dc.subject | Random placement |
dc.subject | Set-associative |
dc.subject | Timing Analysis |
dc.subject | Wcet analysis |
dc.subject | Tolerància als errors (Informàtica) |
dc.subject | Sistemes incrustats (Informàtica) |
dc.title | A cache design for probabilistically analysable real-time systems |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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