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A cache design for probabilistically analysable real-time systems
Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. Probabilistic Timing Analysis (PTA) has emerged as a solution to reduce the amount of information needed to provide tight WCET estimates, although it imposes new requirements on hardware design. At cache level, so far only fully-associative random-replacement caches have been proven to fulfill the needs of PTA, but they are expensive in size and energy. In this paper we propose a cache design that allows setassociative and direct-mapped caches to be analysed with PTA techniques. In particular we propose a novel parametric random placement suitable for PTA that is proven to have low hardware complexity and energy consumption while providing comparable performance to that of conventional modulo placement.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Hardware
Embedded computer systems
Fault-tolerant computing
Amount of information
Cache access
Hardware complexity
Hardware design
Random placement
Set-associative
Timing Analysis
Wcet analysis
Tolerància als errors (Informàtica)
Sistemes incrustats (Informàtica)
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
         

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