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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Aymerich Capdevila, Nivard |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.date | 2013 |
dc.identifier.citation | Aymerich, N.; Rubio, J.A. Study on the optimal distribution of redundancy effort in cross-layer reliable architectures. A: IEEE International Conference on Nanotechnology. "Proceedings of the 13th IEEE International Conference on Nanotechnology: Beijing, China: August 5-8, 2013". Beijing: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 245-249. |
dc.identifier.citation | 978-1-4799-0676-5 |
dc.identifier.citation | 10.1109/NANO.2013.6720848 |
dc.identifier.uri | http://hdl.handle.net/2117/22318 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6720848 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Nanotechnology |
dc.subject | Fault-tolerant computing |
dc.subject | Analytical models |
dc.subject | Computer architecture |
dc.subject | Error probability |
dc.subject | Integrated circuit interconnections |
dc.subject | Redundancy |
dc.subject | Tunneling magnetoresistance |
dc.subject | Nanotecnologia |
dc.subject | Tolerància als errors (Informàtica) |
dc.title | Study on the optimal distribution of redundancy effort in cross-layer reliable architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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