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Study on the optimal distribution of redundancy effort in cross-layer reliable architectures
Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent's Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers. © 2013 IEEE.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Àrees temàtiques de la UPC::Enginyeria electrònica
Fault-tolerant computing
Analytical models
Computer architecture
Error probability
Integrated circuit interconnections
Tunneling magnetoresistance
Tolerància als errors (Informàtica)
Attribution-NonCommercial-NoDerivs 3.0 Spain
Institute of Electrical and Electronics Engineers (IEEE)

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