BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

Home | About RECERCAT | Contact

Català | Castellano

All of RECERCAT

By Communities &
Collections By Defense Date By Authors By Titles By Subject

This Collection

By Defense Date By Authors By Titles By Subject

Statistics

View Statistics All RECERCAT

My RECERCAT

Other repositories directory

RECERCAT Home > Universitat Politècnica de Catalunya > Documents de recerca > View document

To access the full text documents, please follow this link: http://hdl.handle.net/2117/20505

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.contributor.author	Arumi Delgado, Daniel
dc.contributor.author	Rodríguez Montañés, Rosa
dc.contributor.author	Figueras Pàmies, Joan
dc.date	2013
dc.identifier.citation	Arumi, D.; Rodriguez, R.; Figueras, J. BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing. A: IEEE European Test Symposium. "Proceedings of 18th IEEE European Test Symposium". Avignon: Institute of Electrical and Electronics Engineers (IEEE), 2013.
dc.identifier.citation	978-1-4673-6377-8
dc.identifier.citation	10.1109/ETS.2013.6569389
dc.identifier.uri	http://hdl.handle.net/2117/20505
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	http://www.computer.org/csdl/proceedings/ets/2013/6376/00/06569389-abs.html
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica
dc.subject	Integrated circuits
dc.subject	Three-dimensional integrated circuits
dc.subject	built-in self test integrated circuit testing three-dimensional integrated circuits
dc.subject	Circuits integrats
dc.title	BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	built-in self test integrated circuit testing three-dimensional integrated circuits
dc.description.abstract	Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

Show simple item record

All of RECERCAT

This Collection

Statistics

My RECERCAT

Related documents

Other documents of the same author